{"resolved":true,"match_type":"uuid","source_type":"original_book","book_id":"38270854-596f-4a26-8183-db8c968c6020","title":"编码 隐匿在计算机软硬件背后的语言","author":null,"edition":null,"publisher":null,"year":null,"isbn":"9787121181184","requested_by":"printed_page","book":{"source_type":"original_book","book_id":"38270854-596f-4a26-8183-db8c968c6020","id":"38270854-596f-4a26-8183-db8c968c6020","uuid":"38270854-596f-4a26-8183-db8c968c6020","title":"编码 隐匿在计算机软硬件背后的语言","normalized_title":"编码隐匿在计算机软硬件背后的语言","author":null,"edition":null,"publisher":null,"year":null,"isbn":"9787121181184","isbns":["9787121181184","0123456789","6044921875","3039331000","0000000000","0000000000000"],"parsed":true,"ai_readable":true,"document_type":"book","page_count":438,"navigation_url":"https://workshop.closeclaw.top/ai/book/38270854-596f-4a26-8183-db8c968c6020","title_url":"https://workshop.closeclaw.top/ai/title/%E7%BC%96%E7%A0%81%20%E9%9A%90%E5%8C%BF%E5%9C%A8%E8%AE%A1%E7%AE%97%E6%9C%BA%E8%BD%AF%E7%A1%AC%E4%BB%B6%E8%83%8C%E5%90%8E%E7%9A%84%E8%AF%AD%E8%A8%80","fixed_page_url_template":"https://workshop.closeclaw.top/ai/book/38270854-596f-4a26-8183-db8c968c6020/page/{printed_page}","path_api_url_template":"https://workshop.closeclaw.top/api/ai/book/38270854-596f-4a26-8183-db8c968c6020/page/{printed_page}","read_url":"https://workshop.closeclaw.top/api/ai/read/38270854-596f-4a26-8183-db8c968c6020","page_url":"https://workshop.closeclaw.top/api/ai/books/38270854-596f-4a26-8183-db8c968c6020/page","search_url":"https://workshop.closeclaw.top/api/ai/books/38270854-596f-4a26-8183-db8c968c6020/search"},"page":{"printed_page":142,"pdf_page":158,"physical_index":158,"physical_index_base":0,"printed_page_status":"recognized","page_sha256":"44ad3890f497ce91238b963ab060a8669d076cf2f1157028209ab76fbddff151"},"chapter":"编码隐匿在计算机软硬件背后的语言","content":"为了对三个二进制数进行加法运算，我们需要将两个半加器和一个或门做如下连接。\n\n要理解它的工作原理，首先从最左边第一个半加器的输入A和输入B开始，其输出是一个加和及相应的进位。这个和必须与前一列的进位输入相加，然后再把它们输入到第二个半加器中。第二个半加器的输出和是最后的结果。两个半加器的进位输出又被输入到一个或门中。你可能会觉得，这里还需要一个半加法器，这当然是可行的。但是如果你了解了所有的可能性之后，你会发现，两个半加法器的进位输出是不会同时为1的。或门在这里已经足够，因为或门除了在输入都为1的时候以外，其他情况下结果和异或门结果相同。\n\n为了避免重复地画上面的那个图，我们用以下形式来替代上图中的一堆符号，它称为全加器(Full Adder)。\n\n以下表格总结了全加法器所有可能的输入组合以及对应的输出结果。\n\n在本章前面曾经提到过，我们的加法器需要144个继电器。下面就来解释一下这个数目是如何得到的。每个与门、或门和与非门都需要两个继电器，因此一个异或门中就包含6个继电器。一个半加器是由一个异或门和一个与门组成的，因此一个半加器就需要8个继电器。每个全加器由两个半加器和一个或门组成，所以它要18个继电器。我们需要8个全加器来制作8位二进制加法器。因而总共需要144个继电器。\n\n编码—隐匿在计算机软硬件背后的语言\n\n142","previous_page":null,"next_page":143}